BS62LV8000 Datasheet, PDF (5/10 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 1M X 8 bit

BSI
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 ^(1,2,4)
t RC
ADDRESS
D _OUT
t OH
t AA
READ CYCLE2 ^(1,3,4)
CE2
CE1
D _OUT
t ACS2
t ACS1
(5)
t CLZ
READ CYCLE3 ^(1,4)
ADDRESS
OE
CE2
CE1
D _OUT
t RC
t AA
t OE
t ACS2
t OLZ
t ACS1
(5)
t CLZ
BS62LV8000
t OH
t (5)
CHZ
t OH
t ⁽⁵⁾
OHZ
t (1,5)
CHZ
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV8000
5
Revision 2.4
April 2002