BS62LV8000 Datasheet, PDF (1/10 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 1M X 8 bit

BSI ^{Very Low Power/Voltage CMOS SRAM}
1M X 8 bit
BS62LV8000
„ FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
Vcc = 5V C-grade: 45mA (Max.) operation current
I -grade: 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max) at Vcc = 3V
-10 100ns (Max) at Vcc = 3V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
„ GENERAL DESCRIPTION
The BS62LV8000 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.5uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable(CE2) and active LOW output
enable (OE) and three-state output drivers.
The BS62LV8000 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV8000 is available in 44 pin TSOP2 and 48-pin BGA type.
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
Vcc
TEMPERATURE RANGE
BS62LV8000EC
BS62LV8000BC
BS62LV8000EI
BS62LV8000BI
+0 ^O C to +70^OC 2.4V ~ 5.5V
-40 ^O C to +85^OC 2.4V ~ 5.5V
SPEED
( ns )
Vcc=3V
70 / 100
70 / 100
POWER DISSIPATION
STANDBY
( ICCSB1, Max )
Operating
( ICC , Max )
PKG TYPE
Vcc=3V Vcc=5V Vcc=3V Vcc=5V
3uA
30uA
20mA
45mA
TSOP2-44
BGA-48-0810
6uA
100uA 25mA
50mA
TSOP2-44
BGA-48-0810
„ PIN CONFIGURATIONS
A4
1
44
A3
2
43
A2
3
42
A1
4
41
A0
5
40
CE1
6
39
NC
7
38
NC
8
37
DQ0
9
DQ1
10
BS62LV8000EC
36
35
VCC
11
GND
12
BS62LV8000EI
34
33
DQ2
13
32
DQ3
14
31
NC
15
30
NC
16
29
WE
17
28
A19
18
27
A18
19
26
A17
20
25
A16
21
24
A15
22
23
1
2
3
4
5
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
6
A
NC
OE
A0
A1
A2
CE2
B
NC
NC
A3
A4
CE1
NC
C
D0
NC
A5
A6
NC
D4
D
VSS
D1
A17
A7
D5
VCC
E
VCC
D2
VCC
A16
D6
VSS
F
D3
NC
A14
A15
NC
D7
G
NC
NC
A12
A13
WE
NC
„ FUNCTIONAL BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
Vdd
Gnd
Address
22
Input
Buffer
Row
Decoder
2048
Memory Array
2048 X 4096
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
4096
8
Column I/O
Write Driver
Sense Amp
8
512
Column Decoder
18
Address Input Buffer
A11A9 A8 A3 A2 A1 A0A10 A19
H
A18
A8
A9
A10
A11
A19
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV8000
1
Revision 2.4
April 2002