BS616UV1010_06 Datasheet, PDF (4/11 Pages) Brilliance Semiconductor – Ultra Low Power CMOS SRAM 64K X 16 bit

n DATA RETENTION CHARACTERISTICS (T_A = -40^OC to +85^OC)
SYMBOL
PARAMETER
TEST CONDITIONS
VDR
ICCDR⁽³⁾
tCDR
tR
VCC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CE≧VCC-0.2V
VIN≧VCC-0.2V or VIN≦0.2V
CE≧VCC-0.2V
VIN≧VCC-0.2V or VIN≦0.2V
See Retention Waveform
1. VCC=1.5V, TA=25^OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCDR(Max.) is 0.2uA at TA=70^OC.
n LOW V_CC DATA RETENTION WAVEFORM (CE Controlled)
VCC
CE
VCC
tCDR
VIH
Data Retention Mode
VDR≧1.5V
CE≧VCC - 0.2V
BS616UV1010
MIN. TYP. ⁽¹⁾ MAX. UNITS
1.5
--
--
V
--
0.01
0.5
uA
0
--
tRC ⁽²⁾
--
--
ns
--
ns
VCC
tR
VIH
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
CL = 5pF+1TTL
CL = 30pF+1TTL
Output
1 TTL
CL(1)
VCC
GND
ALL INPUT PULSES
90%
10%
→←
Rise Time:
1V/ns
90%
10%
→←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
WAVEFORM INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
R0201-BS616UV1010
4
Revision 2.6
May.
2006