BS62LV4000 Datasheet, PDF (1/10 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 512K X 8 bit

BSI ^{Very Low Power/Voltage CMOS SRAM}
512K X 8 bit
BS62LV4000
„ FEATURES
• Wide Vcc operation voltage : 2.7V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max) at Vcc = 3.0V
-10 100ns (Max) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
„ GENERAL DESCRIPTION
The BS62LV4000 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.5uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE), and active LOW output enable (OE) and three-state
output drivers.
The BS62LV4000 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4000 is available in the JEDEC standard 32 pin
, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
Vcc
TEMPERATURE RANGE
BS62LV4000TC
BS62LV4000STC
BS62LV4000TI
BS62LV4000STI
+0 ^O C to +70^O C
-40^O C to +85^O C
2.7V ~ 3.6V
2.7V ~ 3.6V
SPEED
( ns )
Vcc=3.0V
70 / 100
70 / 100
POWER DISSIPATION
STANDBY
( ICCSB1 , Max )
Operating
( ICC, Max )
Vcc=3.0V
Vcc=3.0V
8uA
20mA
12uA
25mA
„ PIN CONFIGURATIONS
„ FUNCTIONAL BLOCK DIAGRAM
PKG TYPE
TSOP-32
STSOP-32
TSOP-32
STSOP-32
A11 1
A9 2
A8 3
A13 4
WE 5
A17 6
A15 7
VCC 8
A18 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
BS62LV4000TC
BS62LV4000STC
BS62LV4000TI
BS62LV4000STI
32 OE
31 A10
30 CE
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 GND
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
WE
OE
Vdd
Gnd
Address
22
Input
Buffer
Row
Decoder
2048
Memory Array
2048 X 2048
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
2048
8
Column I/O
Write Driver
Sense Amp
8
256
Column Decoder
16
Address Input Buffer
A11 A9 A8 A3 A2 A1 A0 A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV4000
1
Revision 2.2
April. 2001