BCM1250 Datasheet, PDF (2/2 Pages) Broadcom Corporation. – HIGH PERFORMANCE INTEGRATED 64 BIT MULTIPROCESSOR

BCM1250 OVERVIEW
BCM1250 Block Diagram
55 Mbps
55 Mbps
JTAG
Serial
Interface
Serial
Interface
Dual
SMBus
GPIO/
Interrupt/
PCMCIA
Debug/
SB-1 SB-1
512-KB
Bus Trace
D
Core
Core L2 Cache
M
256 Bits
A
ZBbus
D
M
A
Bus runs at 1/2 CPU clock @128 Gbps
Data
Mover
DDR
Memory
Controller
I/O Bridge
Generic Bus
and
Flash I/O
DMA
DMA
DMA
10/100/
1000
MAC
FIFO
10/100/
1000
MAC
10/100/
1000
MAC
FIFO
PCI/HT Bridge
32-Bit
PCI
HT
Host
Bridge
16–50 Gbps
1 Gbps
3 x GMII / 2 x 16-bit FIFO
@ 2 Gbps / @ 6 Gbps
2 Gbps 19.2 Gbps
Broadcom’s first SiByte^TM processor, the BCM1250, is a state-
of-the-art multiprocessor solution targeted at the fast-growing
networking and communications markets.
The BCM1250 is the first MIPS64^TM processor to offer the
industry-leading performance, high functional integration, and
low power levels required by next-generation networking
applications.
The BCM1250 is an intelligent on-chip multiprocessor system
(CMP) consisting of two Broadcom SB-1 high performance
MIPS64^TM CPUs, a shared 512-KB L2 cache, a DDR memory
controller, and integrated I/O. All major blocks of the processor
are connected together via the ZBbus, a high-speed, split-
transaction multiprocessor bus. The bus implements the standard
MESI protocol to ensure coherency between the two CPUs, L2
cache, I/O agents, and memory. Three Gigabit Ethernet MACs
(10/100/1000) enable easy interfacing to LANs. To enable higher
data rates, or in cases where Ethernet protocol processing is not
required, the MACs can be configured as either three 8-bit or two
16-bit packet FIFOs. The high-speed I/O is provided using
HyperTransport^TM (HT) I/O fabric and a 32-bit PCI (rev 2.2) local
bus. Two serial ports are available to use as UARTs for console
ports or asynchronous interface for WAN connections at up to
T3/OC-1 rates (55 Mbps).
To enable low chip-count systems, the BCM1250 also includes a
configurable generic bus that allows glueless connection of a
boot ROM or flash memory and simple I/O peripherals. On-chip
debug, trace, and performance monitoring functions assist both
hardware and software designers in debugging and tuning the
system. The system can be run in either big- or little-endian
mode. The BCM1250 is manufactured in TSMC's 0.13µ process
and is available in an 860 BGA package.
Implementation of MIPS64^TM ISA
The SB-1 CPU core is a high-performance implementation of the
standard MIPS64^TM instruction set architecture (ISA), and
incorporates the MIPS-3D and MIPS-MDMX application
specific extensions (ASEs). The core supports a four-issue
enhanced skew pipeline and can dispatch up to two memory and
two ALU (Integer, Floating Point, MDMX or MIPS-3D)
instructions per cycle.
Broadcom^®, the pulse logo, Connecting Everything^®, SiByte^TM and System I/O^TM are
trademarks of Broadcom Corporation and/or its affiliates in the United States and certain
other countries. All other trademarks mentioned are the property of their respective owners.
®
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2003 by BROADCOM CORPORATION. All rights reserved.
1250-PB09-R 06.13.03
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Web: www.broadcom.com