AA4002 Datasheet, PDF (16/22 Pages) BCD Semiconductor Manufacturing Limited – STEREO 2W AUDIO POWER AMPLIFIER

Data Sheet
STEREO 2W AUDIO POWER AMPLIFIER
AA4002
Application Information (Continued)
signal ride on such reference voltage, the chip can not
work until internal DC bias is set up completely. So the
size of C_B can also affect the chip start-up time, which
is approx linearly proportional to the value of bypass
capacitor. For AA4002, here are the start-up times for
several typical capacitor values.
Table 2. C_B vs. Start-up Time
C_B (µF)
0.47
1.0
2.2
Start-up Time (ms)
300
600
1300
For AA4002 power supply, it is better to use individual
power source generated from voltage regulators split
from video, digital circuit units in system. For
bypassing capacitors, it is recommended to use one
electrolytic capacitor of 4.7µF to 10µF in parallel with
0.1µF ceramic capacitor which is located close to the
part.
Setup Proper Gain, Design Example
The total closed loop gain is determined by three
individual units - input stage, feedback network and
output stage.
Input stage, pass-band gain
A_VIN
=
R_{F ( L / R)}
R_{I (L / R)}
...................................................(9)
Feedback network, Internal pass-band gain, A_VFB=1,
for external gain, see formula 1, 2, 3.
Output stage, for BTL mode, A_VOUT=2, for SE mode,
A_VOUT=1.
So the total pass-band gain of AA4002, A_VTOTAL is,
A_VTOTAL = A_VIN ∗ A_VFB ∗ A_VOUT ........................(10)
According to formulas above, it is easy to plot
Amplitude-Frequency characteristic curve. The lower
corner frequency is dependant on A_VIN, A_VOUT, Bass
Boost feature relies on A_VOUT.
Example
V_DD=5V, R_L=8Ω, BTL configuration, desired output
power each channel, P_O=1.0W, THD+N ≤ 1%.
Input signal, V_IN=1.0VRMS from D-A converter.
Step 1,
To check if the chip can deliver 1W to 8Ω load with the
limitation of THD+N ≤ 1%, V_DD=5V by Figure 6, 15.
Step 2,
If yes, to calculate output voltage, . So total pass-band
gain (ignoring Bass boost feature, low frequency
attenuation caused by AC coupling capacitors,
A_VFB=1x.),
A_VTOTAL=V_OUT/V_IN=2.83x.
Step 3,
A_VIN=A_VTOTAL/( A_VFB*A_VOUT )=2.83/(1*2)=1.415,
R_F(L/R)=A_VIN*R_I(L/R), assuming components values
are given in Figure 28, just changing R_F(L/R) to
20kΩ*1.415=28.3kΩ. Select the closest standard value
28kΩ.
Optimizing CLICK/POP Noise
The AA4002 includes a circuit to suppress CLICK/
POP noise during power up/down transition. In practi-
cal application, the chip can effectively suppress
common mode signal including CLICK/POP noise in
BTL configuration. In SE mode, decreasing the size of
output capacitor (C_OUT) can minish POP noise, which
can also affect low frequency response according to
formula 8 above. Increasing bypass capacitor value
(C_B) can slower ramp of charge, prolong start-up time,
mask most of transient noises before bias voltage is
set-up.
Proper power on/off sequence can also optimize
CLICK/POP noise. The recommended is shown in
Figure 24.
Sep. 2006 Rev. 1. 1
BCD Semiconductor Manufacturing Limited
16