AZT71 Datasheet, PDF (9/14 Pages) Arizona Microtek, Inc – Programmable Capacitive Tuning IC

Arizona Microtek, Inc.
AZT71
Programmable Capacitive Tuning IC
ERASING THE EEPROM
The EEPROM can be erased by initiating a programming cycle with all DA bits set high, including bit9 and bit10. After
the programming cycle, all the EEPROM bits are set low (logical high) except for the check bit (bit0), which remains
high.
Table 7 – Erase sequence for EEPROM
Step
1
Set the V_DD supply voltage to +5.0V
Action
2
Load the programming word bits all high.
3
Set the PV pin to +6V (≥5.6V, ≤6.1V) with the pulse and idle shown in timing diagram (Figure 13)
4
Verify the correct EEPROM contents by reading back the individual bits
bit 0
bit 1
DA
bit0
loaded 1^st
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9 bit 10
bit10
loaded last
EEPROM has
been erased
(no capacitors
selected)
CLK
PV
10ms
min
4µs
min
≥5.6V,
≤6.1V
t
Figure 13 – Programming Sequence for erasing the EEPROM
PROGRAMMING VOLTAGE LIMIT CIRCUIT
Some existing programming circuits use a current source connected to a 6.5 – 8.0 V supply. That circuit produces an
excessive voltage on the PV pin, which can damage the AZT71. A simple modification eliminates the issue and maintains
full programming compatibility with existing programming methods. A 5.6 V, ½ watt Zener, 1N5232B or equivalent,
placed between the PV pin and ground will limit the voltage while still allowing the programming circuit to generate the
current required for programming fuse link type parts.
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May 2012, Rev 1.2