AZT71 Datasheet, PDF (3/14 Pages) Arizona Microtek, Inc – Programmable Capacitive Tuning IC

Arizona Microtek, Inc.
AZT71
Programmable Capacitive Tuning IC
ENGINEERING NOTES
CAPACITOR STRUCTURE
The AZT71 capacitance value is composed of four parallel capacitors banks, C_F is a fixed capacitor value of 6.6pF and
C_hi, C_mid & C_lo are variable capacitors of differing ranges and resolutions as seen in Table 4. Capacitors composing C_hi,
C_mid and C_lo are set with a binary control word through an 11-bit shift register described in PROGRAMMING THE AZT71.
The values of each C_hi, C_mid and C_lo stepping are detailed in the complete Nominal Capacitance Binary Mapping
spreadsheet.
C_Total = C_F + C_hi + C_mid + C_lo
Table 4 - AZT71 Capacitor Structure
Internal
Capacitor
C_F
C_hi
C_mid
C_lo
Total
Min Value
(pF)
6.6
0
0
0
6.6
Max Value
(pF)
6.6
19.2
9.8
1.953
37.553
Step Size
(pF)
n/a
6.4
1.4
0.063
PROGRAMMING THE AZT71
CONTROL WORD
The capacitance in the AZT71 is controlled by an 11-bit shift register with the data input bit definitions shown in Table 5.
The control word data is inputted serially on the rising edge of the CLK signal with bit0 first and bit10 last.
Table 5 - AZT71 Control Word Definition
11-bit Control Word
bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1
C_hi
C_mid
C_lo
MSB
LSB MSB
---
LSB MSB
---
---
---
LSB
bit0
Not Used
The control word mapping is a binary word for each of C_hi, C_mid and C_lo where higher number bits are more significant.
Figure 4 shows the capacitance value mapping for the AZT71. The detailed Nominal Capacitance Binary Mapping can be
located on the AZM website.
www.azmicrotek.com
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May 2012, Rev 1.2