AZP92 Datasheet, PDF (2/7 Pages) List of Unclassifed Manufacturers – ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable

AZP92
SIGNAL DESCRIPTION
PIN/PAD
D/D¯
Q/Q¯
V_BB
BIAS
EN
EN-SEL
DIV-SEL
V_EE
V_CC
FUNCTION
Data Inputs
Data Outputs
Reference Voltage Output
Input Bias Return
Enable/Reset Input
Enable Logic Select
Divide Ratio Select
Negative Supply
Positive Supply
ENABLE TRUTH TABLE
EN-SEL
NC
NC
V_EE
V_EE
20kΩ to V_EE
20kΩ to V_EE
EN
Q
CMOS Low or V_EE
Low
CMOS High, V_CC or NC Data
CMOS Low, V_EE or NC Low
CMOS High or V_CC
Data
PECL Low, V_EE or NC Data
PECL High or V_CC
Low
Q¯
High
Data
High
Data
Data
High
DIVIDE TRUTH TABLE
DIV-SEL
DIVIDE
RATIO
NC
÷1
V_EE1
÷2
1 _{DIV-SEL connection must}
be ≤1Ω.
D
EN ^{(EN-SEL CONNECTED TO}
V_EE VIA 20k RESISTOR)
EN ^{(EN-SEL OPEN OR}
CONNECTED TO V_EE)
Q ^(DIV-SEL
OPEN)
Q ^(DIV-SEL
CONNECTED
TO V_EE)
TIMING DIAGRAM
(PECL)
(CMOS)
April 2007 REV - 3
www.azmicrotek.com
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