G121S1-L02 Datasheet, PDF (15/29 Pages) AZ Displays – 12.1” TFT-LCD module

Issued Date: Jan. 11, 2010
Model No.: G121S1-L02
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
DCLK
Signal
Item
Symbol Min. Typ. Max. Unit
Frequency
Fc
34
40
48.3 MHz
Note
Vertical Active Display Term
Horizontal Active Display Term
Total
Display
Blank
Total
Display
Blank
Tv
610
628
800
Th Tv=Tvd+Tvb
Tvd
--
600
--
Th
Tvb Tv-Tvd 28 Tv-Tvd Th
Th
960 1056 1150 Tc Th=Thd+Thb
Thd
--
800
--
Tc
Thb Th-Thd 256 Th-Thd Tc
NoteΚ(1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be
set to low logic level or ground. Otherwise, this module would operate abnormally.
(2) Frame rate is 60Hz
INPUT SIGNAL TIMING DIAGRAM
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Version 2.0