G121S1-L01 Datasheet, PDF (15/26 Pages) AZ Displays – TFT LCD Approval Specification

DOC No.:14068027
Issued Date: Nov. 07, 2006
Model No.: G121S1-L01
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
LVDS Clock
Vertical Active Display Term
Horizontal Active Display Term
Item
Frequency
Period
Frame Rate
Total
Display
Blank
Total
Display
Blank
Symbol
Fc
Tc
Fr
Tv
Tvd
Tvb
Th
Thd
Thb
Min.
33.4
20.7
56
606
600
Tv-Tvd
920
800
Th-Thd
Typ.
39.7
25.1
60
628
600
28
1056
800
256
Max.
48.3
29.9
75
650
600
Tv-Tvd
1240
800
Th-Thd
Unit
MHz
ns
Hz
Th
Th
Th
Tc
Tc
Tc
Note
-
Tv=Tvd+Tvb
-
-
-
Th=Thd+Thb
-
-
Note (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be
set to low logic level or ground. Otherwise, this module would operate abnormally.
INPUT SIGNAL TIMING DIAGRAM
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Version 3.1