G154I1-LE1 Datasheet, PDF (14/26 Pages) AZ Displays – 15.4” TFT-LCD module

PRODUCT SPECIFICATION
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
DCLK
DE
Item
Frequency
Vertical Total Time
Vertical Addressing Time
Horizontal Total Time
Horizontal Addressing Time
Symbol
1/Tc
TV
TVD
TH
THD
Min.
67.45
810
800
1360
1280
Typ.
71
823
800
1440
1280
Max.
74.55
1000
800
1600
1280
Unit
MHz
TH
TH
Tc
Tc
Note
-
-
-
-
-
Note (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low logic level or ground. Otherwise, this module would operate abnormally.
DE
DCLK
DE
INPUT SIGNAL TIMING DIAGRAM
Tv
TVD
TH
TC
THD
DATA
Version 2.0
18th, Mar., 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited.
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