G150XGE-L04_14 Datasheet, PDF (13/28 Pages) AZ Displays – 15.0” TFT Liquid Crystal Display module

PRODUCT SPECIFICATION
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
Item
Symbol Min. Typ. Max. Unit Note
DCLK
DE
Pixel Clock
Vertical Total Time
Vertical Address Time
Horizontal Total Time
Horizontal Address Time
1/T_C 53.35 65
80 MHz
-
T_V
780 806 1200
T_H
-
T_VD
768 768 768
T_H
-
T_H
1140 1344 1600
T_C
-
T_HD
1024 1024 1024
T_C
-
Note (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low logic level or ground. Otherwise, this module would operate abnormally.
DE
DCLK
DE
DATA
INPUT SIGNAL TIMING DIAGRAM
Tv
TVD
TH
TC
THD
Version 2.0
4 June 2013
The copyright belongs to InnoLux. Any unauthorized use is prohibited.
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