HDSP-2107_10 Datasheet, PDF (9/16 Pages) AVAGO TECHNOLOGIES LIMITED – Eight Character 5 mm and 7 mm Smart Alphanumeric Displays

Electrical Description
Pin Function
RESET (RST, pin 1)
FLASH (FL, pin 2)
ADDRESS INPUTS
(A₀-A₄, pins 3-6, 10)
CLOCK SELECT
(CLS, pin 11)
CLOCK INPUT/OUTPUT
(CLK, pin 12)
WRITE (WR, pin 13)
CHIP ENABLE (CE, pin 17)
READ (RD, pin 18)
DATA Bus (D₀-D₇,
pins 19, 20, 23-28)
GND (SUPPLY) (pin 15)
GND (LOGIC) (pin 16)
V_DD (POWER) (pin 14)
Description
Initializes the display.
FL low indicates an access to the Flash RAM and is unaffected by the
state of address lines A₃-A₄.
Each location in memory has a distinct address. Address inputs (A₀-A₂)
select a specific location in the Character RAM, the Flash RAM or a
particular row in the UDC (User-Defined Character) RAM. A₃-A₄ are used
to select which section of memory is accessed. Table 1 shows the
logic levels needed to access each section of memory.
Table 1. Logic Levels to Access Memory
Section of Memory
FL A₄ A₃
Flash RAM
0XX
UDC Address Register 1 0 0
UDC RAM
10 1
Control Word Register 1 1 0
Character RAM
11 1
A₂ A₁ A₀
Char. Address
Don’t Care
Row Address
Don’t Care
Character Address
Used to select either an internal (CLS = 1) or external (CLS = 0) clock source.
Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays.
Data is written into the display when the WR input is low and the CE input is low.
Must be at a logic low to read or write data to the display and must go high between
each read and write cycle.
Data is read from the display when the RD input is low and the CE input is low.
Used to read from or write to the display.
Analog ground for the LED drivers.
Digital ground for internal logic.
Positive power supply input.
9