HCPL-0872 Datasheet, PDF (9/12 Pages) AVAGO TECHNOLOGIES LIMITED – Digital Interface IC

Digital Interface Configuration
Configuration Registers
The Digital Interface IC contains four 6-bit configuration
registers that control its behavior. The two LSBs of any
byte clocked into the serial configuration port (CDAT,
CCLK, CLAT) are used as address bits to determine which
register the data will be loaded into. Registers 0 and 1
(with address bits 00 and 01) specify the conversion and
offset calibration modes of channels 1 and 2, register 2
(address bits 10) specifies the behavior of the adjustable
threshold circuit, and register 3 (address bits 11) specifies
which pre-trigger mode to use for channel 1. These
registers are illustrated in Table 1 below, with default
values indicated in bold italic type. Note that there are
several reserved bits, which should always be set low and
that the configuration registers should not be changed
during a conversion cycle.
Conversion Mode
The conversion mode determines the speed/resolution
trade-off for the Isolated A/D converter. The four MSBs
of registers 0 and 1 determine the conversion mode for
the appropriate channel. The bit settings for choosing a
particular conversion mode are shown in Table 2 below.
Combinations of data bits not specified in Table 2 below
are not recommended.
Table 1. Register Configuration.
Configuration Data Bits
Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Channel 1 Conversion Mode
Channel 1
Offset Cal
High
High
Low
Low
Low
1
Channel 2 Conversion Mode
Channel 2
Offset Cal
High
High
Low
Low
Low
Threshold Detection
2
Time
High
Low
Low
Threshold Level
Low
Low
3
Pre-Trigger Mode
Reserved
Low
Low
Low
Low
Low
Notes: Bold italic type indicates Default values. Reserved bits should be set low.
Bit 2
Reserved
Low
Reserved
Low
Low
Low
Address Bit
Bit 1
Bit 0
Low
Low
Low
High
High
High
Low
High
Table 2. Conversion Mode Configuration.
Conversion
Mode
1
2
3
4
5
Bit 7
Low
Low
High
High
High
Notes: Bold italic type indicates Default values.
Configuration Data Bits
Bit 6
Bit 5
High
Low
Low
High
High
High
High
Low
Low
High
Bit 4
High
High
Low
Low
Low