HCPL-0872 Datasheet, PDF (11/12 Pages) AVAGO TECHNOLOGIES LIMITED – Digital Interface IC

Table 3. Pre-Trigger Mode Configuration.
Pre-Trigger
Mode
Configuration Data Bits
Bit 7
Bit 6
0
Low
Low
1
Low
High
2
High
Don’t Care
Notes: Bold italic type indicates Default values.
5. Send another configuration byte to the appropriate
register for the selected channel, setting bit 3 low to
disable calibration mode and setting bits 4 through 7
to select the desired conversion mode for subsequent
conversions on that channel.
To calibrate both channels, perform the above sequence
for each channel. The offset calibration sequence can be
performed as often as needed. Table 4 below summarizes
how to turn the offset calibration mode on or off using
bit 3 of configuration registers 0 and 1.
Table 4. Offset Calibration Configuration.
Offset Calibration
Mode
Configuration Data Bits
Bit 3
Off
Low
On
High
Notes: Bold italic type indicates Default values.
Offset Calibration
The offset calibration circuit can be used to separately
calibrate the offsets of both channels 1 and 2. The offset
calibration circuit contains a separate offset register for
each channel. After an offset calibration sequence, the
offset registers will contain a value equal to the measured
offset, which will then be subtracted from all subsequent
conversions. A hardware reset (bringing the RESET pin
high for at least 100 ns) is required to reset the offset
calibration registers to zero.
The following sequence is recommended for performing
an offset calibration:
1. Select the appropriate channel using the CHAN pin
(low = channel 1, high = channel 2).
2. Force zero volts at the input of the selected isolated
modulator.
3. Send a configuration data byte to the appropriate reg-
ister for the selected channel (register 0 for channel 1,
register 1 for channel 2). Bit 3 of the configuration byte
should be set high to enable offset calibration mode
and bits 4 through 7 should be set to select conversion
mode 1 to achieve the highest resolution measurement
of the offset.
4. Perform one complete conversion cycle by bringing
CS low until SDAT goes high, indicating completion of
the conversion cycle. Because bit 3 of the configura-
tion has been set high, the uncalibrated output data
from the conversion will be stored in the appropriate
offset calibration register and will be subtracted from
all subsequent conversions on that channel. If multiple
conversion cycles are performed while the offset cali-
bration mode is enabled, the uncalibrated data from
the last conversion cycle will be stored in the offset
calibration register.
Over-Range Detection
The over-range detection circuit allows fast detection
of when the magnitude of the input signal on channel
1 is near or beyond full-scale, causing the OVR1 output
to go high. This circuit can be very useful in current-
sensing applications for quickly detecting when a short-
circuit occurs. The over-range detection circuit works
by detecting when the modulator output data has not
changed state for at least 25 clock cycles in a row, indi-
cating that the input signal is near or beyond full-scale,
positive or negative. Typical response time to over-range
signals is less than 3µs.
The over-range circuit actually begins to indicate an over-
range condition when the magnitude of the input signal
exceeds approximately 250 mV; it starts to generate
periodic short pulses on OVR1, which get longer and
more frequent as the input signal approaches full scale.
The OVR1 output stays high continuously when the input
is beyond full-scale.
The over-range detection circuit continuously monitors
channel 1 independent of which channel is selected with
the CHAN signal. This allows continuous monitoring of
channel 1 for faults while converting an input signal on
channel 2.