AFBR-732BZ Datasheet, PDF (7/22 Pages) AVAGO TECHNOLOGIES LIMITED – Ultra Short Link Pluggable Parallel Fiber Optic Modules, Transmitter and Receiver

Receiver Electrical Characteristics
(T_C = 0 °C to +80 °C, V_CC = 3.3 V ± 5%, Typical T_C = +40 °C, V_CC = 3.3 V)
Parameter
Symbol Min.
Typ.
Max.
Unit
Reference
(Conditions)
Supply Current
I_CCR
400
445
mA
1, Fig. 5
Power Dissipation
P_DISR
1.3
1.55
W
Differential Output Impedance
Z_OUT
80
100
120
W
2, Fig. 8, 10
Data Output Differential Peak-to-Peak
DV_DOUTP-P
450
600
750
mV_P-P
3, Figs. 7, 8
Voltage Swing
Inter-channel Skew
100
150
ps
4
Differential Data Output Rise/Fall Time
tr/tf
110
150
ps
Signal Detect Assert Time (OFF-to-ON)
tSDA
170
µs
De-assert Time (ON-to-OFF) t_SDD
190
µs
Control I/O
Output Voltage Low
V_OL
V_EE
0.4
V
LVTTL & LVCMOS Output Voltage High
V_OH
2.5
3.1
V_CC
V
Compatible
5
6
7
(I_OL = 4.0 mA)
(I_OH = -0.5 mA)
Notes:
1. I_CCR is the dc supply current, dependent upon the number of active channels, where the Data Outputs are ac coupled with capacitors between the
outputs and any resistive terminations. See Figure 7 for recommended termination.
2. Measured over the range 4 MHz to 2 GHz.
3. DV_DOUTP-P = DV_DOUTH – DV_DOUTL, where DV_DOUTH = High State Differential Data Output Voltage and DV_DOUTL = Low State Differential Data Output
Voltage. DV_DOUTH and DV_DOUTL = V_DOUT+ – V_DOUT–, measured with a 100 W differential load connected with the recommended coupling capacitors and
with a 2500 MBd, 8B10B serial encoded data pattern.
4. Inter-channel Skew is defined for the condition of equal amplitude, zero ps skew input signals. Input power at –10 dBm.
5. Rise and Fall Times are measured between the 20% and 80% levels using a 500 MHz square wave signal.
6. The Signal Detect output will change from logic “0” (Low) to “1” (High) within the specified assert time for a step transition in optical input power from
the de-asserted condition to the specified asserted optical power level on all 12 channels.
7. The Signal Detect output will change from logic “1” (High) to “0” (Low) within the specified de-assert time for a step transition in optical input power
from the specified asserted optical power level to the de-asserted condition on any 1 channel.
7