HDSP-2131_07 Datasheet, PDF (6/16 Pages) AVAGO TECHNOLOGIES LIMITED – Eight Character 5.0 mm (0.2 inch) Glass/Ceramic Intelligent 5x7 Alphanumeric Displays for Military Applications

AC Timing Characteristics over Temperature Range
V_DD = 4.5 to 5.5 V unless otherwise specified
Reference
Number
Symbol
Description
1
t_ACC
Display Access Time
Write
Read
2
t_ACS
Address Setup Time to Chip Enable
3
t_CE
Chip Enable Active Time^[2,3]
Write
Read
4
t_ACH
Address Hold Time to Chip Enable
5
t_CER
Chip Enable Recovery Time
6
t_CES
Chip Enable Active Prior to Rising Edge of^[1,2]
Write
Read
7
t_CEH
Chip Enable Hold Time to Rising Edge of
Read/Write Signal^[2,3]
8
t_W
Write Active Time^[2,3]
9
t_WD
Data Valid Prior to Rising Edge of Write Signal
10
t_DH
Data Write Hold Time
11
t_R
Chip Enable Active Prior to Valid Data
12
t_RD
Read Active Prior to Valid Data
13
t_DF
Read Data Float Delay
–
t_RC
Reset Active Time^[4]
Min.^[1]
210
230
10
140
160
20
60
140
160
0
100
50
20
160
75
10
300
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Worst case values occur at an IC junction temperature of 150°C.
2. For designers who do not need to read from the display, the Read line can be tied to V_DD and the Write and Chip Enable lines can be tied together.
3. Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM, regardless of the
logic levels of the WR and RD lines.
4. The display must not be accessed until after 3 clock pulses (110 µs min. using the internal refresh clock) after the rising edge of the reset line.
6