HDSP-2131_07 Datasheet, PDF (12/16 Pages) AVAGO TECHNOLOGIES LIMITED – Eight Character 5.0 mm (0.2 inch) Glass/Ceramic Intelligent 5x7 Alphanumeric Displays for Military Applications

UDC RAM and UDC Address Register
Figure 3 shows the logic levels
needed to access the UDC RAM
and the UDC Address Register.
The UDC Address Register is eight
bits wide. The lower four bits (D₀-
D₃) are used to select one of the
16 UDC locations. The upper four
bits (D₄-D₇) are not used. Once
the UDC address has been stored
in the UDC Address Register, the
UDC RAM can be accessed.
To completely specify a 5 x 7
character requires eight write
cycles. One cycle is used to store
the UDC RAM address in the UDC
Address Register. Seven cycles
are used to store dot data in the
UDC RAM. Data is entered by
rows. One cycle is needed to
access each row. Figure 4 shows
the organization of a UDC
character assuming the symbol to
be stored is an “F.” A₀-A₂ are used
to select the row to be accessed
and D₀-D₄ are used to transmit
the row dot data. The upper three
bits (D₅-D₇) are ignored. D₀ (least
significant bit) corresponds to the
right most column of the 5 x 7
matrix and D₄ (most significant
bit) corresponds to the left most
column of the 5 x 7 matrix.
Flash RAM
Figure 5 shows the logic levels
needed to access the Flash RAM.
The Flash RAM has one bit
associated with each location of
the Character RAM. The Flash
input is used to select the Flash
RAM. Address lines A₃-A₄ are
ignored. Address lines A₀-A₂ are
used to select the location in the
Flash RAM to store the attribute.
D₀ is used to store or remove the
flash attribute. D₀ = “1” stores the
attribute and D₀ = “0” removes the
attribute.
RST CE WR RD
0 0 UNDEFINED
0 1 WRITE TO DISPLAY
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1 0 READ FROM DISPLAY
1 1 UNDEFINED
CONTROL SIGNALS
FL A₄ A₃ A₂ A₁ A₀
1 0 0XXX
UDC ADDRESS REGISTER ADDRESS
D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
XX X X
UDC CODE
UDC ADDRESS REGISTER DATA FORMAT
RST CE WR RD
0 0 UNDEFINED
1
0
0
1 WRITE TO DISPLAY
1 0 READ FROM DISPLAY
1 1 UNDEFINED
CONTROL SIGNALS
FL A₄ A₃
10 1
UDC RAM ADDRESS
A₂ A₁ A₀
ROW SELECT
000 = ROW 1
110 = ROW 7
D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
XX X
DOT DATA
UDC RAM
C
C
DATA FORMAT
O
O
L
L
1
5
0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE
Figure 3. Logic levels to access a UDC character.
CCCCC
OOOOO
LLLLL
12345
D₄ D₃ D₂ D₁ D₀
11111
10000
10000
11110
10000
10000
10000
IGNORED
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
UDC CHARACTER
•••••
•
•
••••
•
•
•
HEX CODE
1F
10
10
1D
10
10
10
0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED
Figure 4. Data to load “F” into the UDC RAM.
When the attribute is enabled
through bit 3 of the Control Word
and a "1" is stored in the Flash
RAM, the corresponding character
will flash at approximately 2 Hz.
The actual rate is dependent on
the clock frequency. For an
external clock the flash rate can
be calculated by dividing the clock
frequency by 28,672.
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