ACPL-32JT Datasheet, PDF (6/18 Pages) AVAGO TECHNOLOGIES LIMITED – Controller for Isolated DC-DC Converter, Integrated IGBT Desat

DESAT Fault Detection Blanking Time
After the IGBT is turned on, the DESAT fault detection circuitry must remain disabled for a short time period to allow
the collector voltage to fall below the DESAT threshold. This time period, called the total DESAT blanking time, is con-
trolled by the both internal DESAT blanking time t_{DESAT(BLANKING)} and external blanking time, determined by the internal
charge current, the DESAT voltage threshold, and the external DESAT capacitor.
The total blanking time is calculated in terms of internal blanking time (t_{DESAT(BLANKING)}), external capacitance (C_BLANK),
FAULT threshold voltage (V_DESAT), and DESAT charge current (I_CHG) as
t_BLANK = t_{DESAT(BLANKING)} + C_BLANK × V_DESAT / I_CHG
Description of Gate Driver and Miller Clamping
The gate driver is directly controlled by the LED current. When the LED current is driven high, ACPL-32JT can then deliver
a 2.5 A sourcing current to drive the IGBT’s gate. When the LED is switched off, the gate driver can provide a 2.5 A sinking
current to quickly switch off the gate. The additional Miller clamping pull-down transistor is activated when the output
voltage reaches about 2 V with respect to V_EE2 to provide a low impedance path to the Miller current, as shown in Figure 6.
I_F
V_O
V_GATE
Figure 4. Gate Drive Signal Behavior
Description of Under Voltage Lock Out
Insufficient gate voltage to IGBT can increase turn on resistance of IGBT, resulting in large power loss and IGBT damage
due to high heat dissipation. ACPL-32JT monitors the output power supply constantly. When output power supply is
lower than under voltage lockout (UVLO) threshold gate driver output will shut off to protect IGBT from low voltage bias.
During power up, the UVLO feature forces the ACPL‑32JT’s output low to prevent an unwanted turn-on at lower voltage.
V _CC1
V _CC2
LED I_F
V_O
V CC1_TH
V _UVLO-
t_{UVLO_OFF}
V UVLO+
t_{UVLO_ON}
/FAULT
/UVLO
t_{PHL_UVLO}
Figure 5. Circuit Behaviors at Power-up and Power down
t_{PLH_UVLO}
Description of Over-Voltage Protection
If V_CC2 is greater than the specified V_CC2 OverVoltage Protection Threshold, then the transistor at the SW pin on the
primary side will shut down and the DC/DC flyback conversion will stop.
6