AJAV-5601 Datasheet, PDF (4/6 Pages) AVAGO TECHNOLOGIES LIMITED – W-CDMA/HSPA Band I Power Amplifier

Application Information
Low current <10µA
Pin 1 can be directly
connected to VBAT
VBAT
1 _VBAT
RF IN
2 _RFI
VM1
3 _VM1
VM0
4 _VM0
VEN
5 _VEN
VBAT
4.7 µF
0603
AJAV-5601
VBAT ¹⁰
RFO ⁹
CPLI ⁸
GND ⁷
CPLO ⁶
GND Paddle
10 pF
0402
RF OUT
CPLI
CPLO
Figure 1. Typical Single-Band Application Circuit
The AJAV-5601 is a complete, high-performance 3G Band
I power amplifier (PA) implemented in a standard CMOS
process. The AJAV-5601 delivers low current and inte-
grates TX filtering that produces the best noise in the in-
dustry. Only a single RF bypass capacitor is required, en-
abling a very low bill-of-materials (BOM). The AJAV-5601 is
fully compliant with W-CDMA, HSPA and HSPA+ standards
through 3GPP Release 7 and supports Power Class 3 and 4.
Figure 1 shows the typical application circuit. The AJAV-
5601 supports three power modes controlled by a stan-
dard CMOS interface enabling a direct connection to the
baseband with no level shifters. The VEN, VM0 and VM1
power control pins are high impedance with logic levels
defined in Table 2.
The AJAV-5601 may be powered by a single direct con-
nection to the battery, or controlled with an external DC-
DC converter. All power supply current flows through pin
10. Pin 1 is a low current input that can be directly con-
nected to VBAT or any other high level signal. No external
switches, isolation inductors, or bypass capacitors are re-
quired on Pin 1.
Standard RF practice should be followed for the PCB layout
of the RF traces for pins 2, 6, 8, and 9. Multiple vias should
be placed underneath the GND paddle to create a low re-
sistance path to ground and to ensure good heat conduc-
tion. Refer to Application Note 5565, (AV02-4080EN) AJAV-
5xxx PCB Guidelines, for additional information.
The AJAV-5601 features an integrated directional coupler
that can be daisy chained through the CPLI and CPLO
ports. For best performance, at least one port should see
a 50 Ω path to GND. The CPLI port accepts an RF input or
can be terminated. The CPLO port provides the coupled
RF output that can be passed to the RF detector, termi-
nated or passed to the next PA in the daisy chain.
The AJAV-5601 includes integrated TX filtering that en-
sures excellent receiver sensitivity. As the RF signal passes
through the PA, the unwanted out-of-band noise pro-
duced by the transceiver is filtered out. Furthermore, the
thermal noise at the PA output is greatly reduced below
the level of a conventional GaAs PA. The resulting signal
at the output of the AJAV-5601 is spectrally very clean, en-
suring the best receiver sensitivity and producing minimal
interference to other radios in the system.
The AJAV-5601 integrates the RF Front-End Control Inter-
face (RFFE) version 1.1 from the MIPI Alliance. This option-
al interface is available for advanced features including
power control. For additional information on using the
MIPI interface, please contact your Avago support.
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