HCPL-4506-000E Datasheet, PDF (19/21 Pages) AVAGO TECHNOLOGIES LIMITED – Intelligent Power Module and Gate Drive Interface Optocouplers

+5 V
I_LED1
310 Ω
CMOS
+5 V
I_LED2
310 Ω
CMOS
HCPL-4506
1
2
20 kΩ
8
0.1 µF
7
3
6
4
5
SHIELD
HCPL-4506
1
2
20 kΩ
8
0.1 µF
7
3
6
4
5
SHIELD
V_CC1
20 kΩ
V_OUT1
V_CC2
20 kΩ
V_OUT2
HCPL-4506
HCPL-4506
HCPL-4506
HCPL-4506
HCPL-4506
IPM
Q1
Q2
Figure 24. Typical application circuit.
HCPL-4506 fig 28
+HV
M
-HV
I_LED1
V_OUT1
V_OUT2
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
I_LED2
t_{PLH MAX.}
t_PHL
MIN.
PDD* MAX. =
(t_PLH-t_PHL) _{MAX. =} t_{PLH MAX. -} t_{PHL MIN.}
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
HCPL-4506 fig 29
Figure 25. Minimum LED skew for zero dead time.
I_LED1
V_OUT1
V_OUT2
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
I_LED2
t_PLH
MIN.
t_PLH
MAX.
PDD*
MAX.
t_PHL
MIN.
t_PHL
MAX.
MAX.
DEAD TIME
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
= (t_{PLH MAX. -} t_{PLH MIN.}) + (t_{PHL MAX. -} t_{PHL MIN.})
= (t_{PLH MAX. -} t_{PHL MIN.}) - (t_{PLH MIN. -} t_{PHL MAX.})
= PDD* MAX. - PDD* MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
HCPL-4506 fig 30
Figure 26. Waveforms for dead time calculation.
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