HCPL-0931-500E Datasheet, PDF (13/14 Pages) AVAGO TECHNOLOGIES LIMITED – High Speed Digital Isolators

Propagation Delay, Pulse Width Distortion and Propaga-
tion Delay Skew
Propagation Delay is a figure of merit, which describes
how quickly a logic signal propagates through a system
as illustrated in Figure 3.
INPUT
V_IN
OUTPUT
V_OUT
tPLH
90%
10%
50%
tPHL
90%
10%
5 V CMOS
0V
VOH
2.5 V CMOS
VOL
Figure 3. Timing Diagrams to Illustrate Propagation Delay, t_PLH and t_PHL.
As illustrated in Figure 4, if the inputs of two or more
devices are switched either ON or OFF at the same time,
t_PSK is the difference between the minimum propagation
delay, either t_PLH or t_PHL, and the maximum propagation
delay, either t_PLH or t_PHL.
V_IN
50%
V_OUT
2.5 V
CMOS
t_PSK
The propagation delay from low to high, t_PLH, is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low,
t_PHL, is the amount of time required for the ­input signal to
propagate to the output, causing the output to change
from high to low.
V_IN
50%
V_OUT
2.5 V
CMOS
Figure 4. Timing Diagrams to Illustrate P­ ropagation Delay Skew.
Pulse Width Distortion, PWD, is the difference between t_PHL
and t_PLH and often determines the maximum data rate ca-
pability of a transmission system. PWD can be expressed in
percent by dividing the PWD (in ns) by the minimum pulse
width (in ns) being transmitted. Typically, PWD on the order
of 20 – 30% of the minimum pulse width is tolerable.
Propagation Delay Skew, t_PSK, and Channel-to-Channel
Skew, t_CSK, are critical parameters to consider in parallel
data transmission applications where s­ ynchronization of
signals on parallel data lines is a concern. If the parallel
data is being sent through channels of the digital
isolators, differences in propagation delays will cause
the data to arrive at the o­ utputs of the digital isolators
at different times. If this difference in propagation delay
is large enough, it will limit the maximum transmission
rate at which parallel data can be sent through the digital
isolators.
t_PSK is defined as the difference between the minimum and
maximum propagation delays, either t_PLH or t_PHL, among two
or more devices which are operating u­ nder the same con-
ditions (i.e., the same drive current, ­supply voltage, output
load, and operating temperature). t_CSK is defined as the
difference between the minimum and maximum propaga-
tion delays, either t_PLH or t_PHL, among two or more channels
within a single device (applicable to dual and quad channel
­devices) which are operating under the same conditions.
As mentioned earlier, t_PSK, can determine the maximum
parallel data transmission rate. Figure 5 shows the timing
diagram of a typical parallel data transmission application
with both the clock and data lines being sent through the
digital isolators. The figure shows data and clock signals at
the inputs and o­ utputs of the digital isolators. In this case,
the data is clocked off the rising edge of the clock.
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t_PSK
t_PSK
Figure 5. Parallel Data Transmission.
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