HCPL-0931-500E Datasheet, PDF (11/14 Pages) AVAGO TECHNOLOGIES LIMITED – High Speed Digital Isolators

Mixed 5V/3.3V or 3.3V/5V operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at T_A=+25°C, V_DD1 = +5.0 V, V_DD2 = +3.3V.
Parameter
Symbol
Min.
Typ.
Max. Units Test Conditions
HCPL-9000/-0900
I_DD1
HCPL-9030/-0930
0.012
0.012
HCPL-9031/-0931 2.5
HCPL-900J/-090J 0.024
HCPL-901J/-091J 5.0
HCPL-902J/-092J 2.5
0.018
0.018
3.0
0.036
6.0
3.0
Quiescent Supply Current 2
I_DD2 mA V_IN = 0V
HCPL-9000/-0900
5.0
6.0
HCPL-9030/-0930
5.0
6.0
HCPL-9031/-0931 2.5
3.0
HCPL-900J/-090J 8.0
12.0
HCPL-901J/-091J 5.0
6.0
HCPL-902J/-092J
6.0
9.0
Logic Input Current
I_IN
-10
10
Logic High Output Voltage
V_OH
V_DD2– 0.1
V_DD2

0.8*V_DD2
V_DD2 – 0.5
Logic Low Output Voltage
V_OL
0
0.1

0.5
0.8
Switching Specifications
µA
V
I_OUT= -20 µA, V_IN= V_IH
V
I_OUT= -4 mA, V_IN= V_IH
V
I_OUT= 20 µA, V_IN= V_IL
V
I_OUT= 4 mA, V_IN= V_IL
Maximum Data Rate
100
110
Clock Frequency
fmax
50
MBd C_L = 15 pF
MHz
Propagation Delay Time to Logic
t_PHL
12
Low Output
18
ns
Propagation Delay Time to Logic
t_PLH
12
High Output
18
ns
Pulse Width
t_PW
10
Pulse Width Distortion^[1]
|PWD|
2
3
|t_PHL – t_PLH|
Propagation Delay Skew^[2]
t_PSK
4
6
Output Rise Time (10 – 90%)
t_R
2
4
Output Fall Time (10 – 90%)
t_F
2
4
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
t_PHZ
3
5
Low to High Impedance
t_PLZ
3
5
High Impedance to High
t_PZH
3
5
High Impedance to Low
t_PZL
3
5
Channel-to-Channel Skew
t_CSK
2
3
(Dual and Quad Channels)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Common Mode Transient Immunity |CM_H|
15
18
(Output Logic High or Logic Low)^[3] |CM_L|
kV/µs V_cm = 1000V
Notes:
1. PWD is defined as |t_PHL -t_PLH|. %PWD is equal to the PWD divided by the pulse width.
2. t_PSK is equal to the magnitude of the worst case difference in t_PHL and/or t_PLH that will be seen between units at 25°C.
3. CM_H is the maximum common mode voltage slew rate that can be sustained while maintaining V_OUT > 0.8V_DD2. CM_L is the maximum common mode
input voltage that can be sustained while maintaining V_OUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
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