AS4LC1M16 Datasheet, PDF (10/22 Pages) Austin Semiconductor – 1 MEG x 16 DRAM

AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
NOTES
1. All voltages referenced to VSS.
2. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0˚C ≤ TA ≤ 70˚C) is assured.
3. An initial pause of 100µs is required after power-up
followed by eight ?R?A/S refresh cycles (?R?A/S ONLY or
CBR with ?W/E HIGH) before proper device operation
is assured. The eight ?R?A/S cycle wake-ups should be
repeated any time the ^tREF refresh requirement is
exceeded.
4. NC pins are assumed to be left floating and are not
tested for leakage.
5. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. VCC = +3.0V; f = 1 MHz.
9. AC characteristics assume ^tT = 2.5ns.
10. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
11. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
12. Measured with a load equivalent to two TTL gates,
100pF and VOL = 0.8V and VOH = 2.0V.
13. ^tWCS, ^tRWD, ^tAWD and ^tCWD are not restrictive
operating parameters. ^tWCS applies to EARLY
WRITE cycles. ^tRWD, ^tAWD and ^tCWD apply to
READ-MODIFY-WRITE cycles. If ^tWCS ≥ ^tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If ^tWCS < ^tWCS (MIN) and ^tRWD ≥
t_{RWD (MIN),} t_{AWD ≥} t_{AWD (MIN) and} t_{CWD ≥}
t_{CWD (MIN), the cycle is a READ-MODIFY-WRITE}
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. ?O/E held HIGH
and ?W/E taken LOW after ?C?A/S goes LOW results in a
LATE WRITE (?O/E-controlled) cycle. ^tWCS, ^tRWD,
t_{CWD and} t_{AWD are not applicable in a LATE}
WRITE cycle.
14. Assumes that ^tRCD ≥ ^tRCD (MAX).
15. If ?C?A/S is LOW at the falling edge of ?R?A/S, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, ?C?A/S must be
pulsed HIGH for ^tCP.
16. These parameters are referenced to ?C?A/S leading edge
in EARLY WRITE cycles and ?W/E leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
17. If ?O/E is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted. Additionally, ?W/E
must be pulsed during ?C?A/S HIGH time in order to
place I/O buffers in High-Z.
18. LATE WRITE and READ-MODIFY-WRITE cycles
must have both ^tOD and ^tOEH met (?O/E HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously read data if ?C?A/S
remains LOW and ?O/E is taken back LOW after ^tOEH
is met. If ?C?A/S goes HIGH prior to ?O/E going back
LOW, the DQs will remain open.
19. Assumes that ^tRCD < ^tRCD (MAX). If ^tRCD is greater
than the maximum recommended value shown in this
table, ^tRAC will increase by the amount that ^tRCD
exceeds the value shown.
20. ^tOFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL. It is referenced from the
rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
21. Operation within the ^tRAD (MAX) limit ensures that
t_{RAC (MIN) and} t_{CAC (MIN) can be met.} t_RAD
(MAX) is specified as a reference point only; if ^tRAD
is greater than the specified ^tRAD (MAX) limit, then
access time is controlled exclusively by ^tAA, provided
t_{RCD is not exceeded.}
22. Operation within the ^tRCD (MAX) limit ensures that
t_{RAC (MAX) can be met.} t_{RCD (MAX) is specified as}
a reference point only; if ^tRCD is greater than the
specified ^tRCD (MAX) limit, then access time is
controlled exclusively by ^tCAC, provided ^tRAD is not
exceeded.
23. Either ^tRCH or ^tRRH must be satisfied for a READ
cycle.
24. The first ?C?A/Sx edge to transition LOW.
25. Output parameter (DQx) is referenced to correspond-
ing ?C?A/S input; DQ1-DQ8 by ?C?A/S/L and DQ9-DQ16
by ?C?A/S?H.
26. Each ?C?A/Sx must meet minimum pulse width.
27. The last ?C?A/Sx edge to transition HIGH.
28. Last falling ?C?A/Sx edge to first rising ?C?A/Sx edge.
29. Last rising ?C?A/Sx edge to first falling ?C?A/Sx edge.
30. Last rising ?C?A/Sx edge to next cycle’s last rising ?C?A/Sx
edge.
31. Last ?C?A/Sx to go LOW.
32. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, ?W/E = LOW and
?O/E = HIGH.
AS4LC1M16
REV. 3/97
DS000020
2-102
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.