AS4LC1M16 Datasheet, PDF (1/22 Pages) Austin Semiconductor – 1 MEG x 16 DRAM

AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
DRAM
PRELIMINARY
1 MEG x 16 DRAM
3.3V, EDO PAGE MODE,
OPTIONAL EXTENDED REFRESH
AVAILABLE AS MILITARY
SPECIFICATIONS
• MIL-STD 883
• SMD Planned
FEATURES
• JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All device pins are TTL-compatible
• Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR),
HIDDEN
• BYTE WRITE access cycles
• 1,024-cycle refresh (10 row-, 10 column-addresses)
• Low power, 0.3mW standby; 180mW active, typical
• Extended Data-Out (EDO) PAGE access cycle
• 5V-tolerant I/Os (5.5V maximum VIH level)
OPTIONS
• Timing
60ns access (Contact Factory)
70ns access
80ns access
MARKING
-6
-7
-8
• Refresh Rate
Standard 16ms period
None
• Packages
Ceramic SOJ
Ceramic Gull Wing
Ceramic LCC
ECJ No. 506
ECG No. 604
EC No. 213
KEY TIMING PARAMETERS
SPEED
-6
-7
-8
t_RC
105ns
125ns
150ns
t_RAC
60ns
70ns
80ns
t_PC
25ns
30ns
40ns
t_AA
30ns
35ns
40ns
t_CAC
15ns
20ns
20ns
t_CAS
12ns
12ns
20ns
GENERAL DESCRIPTION
The AS4LC1M16 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x16 con-
figuration. The AS4LC1M16 has both BYTE WRITE and
WORD WRITE access cycles via two ?C?A/S pins (?C?A?S/L and
?C?A?S?H). These function in a similar manner to a single ?C?AS
of other DRAMs in that either ?C?A?S/L or C? ?A?S?H will generate
PIN ASSIGNMENT (Top View)
44/50-Pin SOJ/LCC/Gull Wing
450mil
Vcc
1
DQ1
2
DQ2
3
DQ3
4
DQ4
5
Vcc
6
DQ5
7
DQ6
8
DQ7
9
DQ8
10
NC
11
NC
15
NC
16
WE
17
RAS
18
NC
19
NC
20
A0
21
A1
22
A2
23
A3
24
Vcc
25
50
Vss
49
DQ16
48
DQ15
47
DQ14
46
DQ13
45
Vss
44
DQ12
43
DQ11
42
DQ10
41
DQ9
40
NC
36
NC
35
CASL
34
CASH
33
OE
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
Vss
an internal ?C?A/S.
The AS4LC1M16 ?C?A/S function and timing are deter-
mined by the first ?C?A/S (?C?A?S/L or ?C?A?S?H) to transition LOW
and the last ?C?A/S to transition back HIGH. Use of only one
ofthetworesultsinaBYTEWRITEcycle.?CA? S? L/ transitioning
LOW selects an access cycle for the lower byte (DQ1-DQ8)
and ?C?A?S?H transitioning LOW selects an access cycle for the
upper byte (DQ9-DQ16).
Each bit is uniquely addressed through the 20 address bits
during READ or WRITE cycles. These are entered 10 bits
(A0 -A9) at a time. ?R?A/S is used to latch the first 10 bits and
?C?A/S the latter 10 bits. The ?C?A/S function also determines
whether the cycle will be a refresh cycle (?R?A/S ONLY) or an
active cycle (READ, WRITE or READ WRITE) once ?R?A/S
goes LOW.
AS4LC1M16
REV. 3/97
DS000020
2-93
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.