SD6830 Datasheet, PDF (14/34 Pages) AUK corp – 4BIT MICROCONTROLLER

SD6830
SD6830
Figure 6-6. Rest structure and Release Timing for STOP Mode to Normal Mode
6.14 OSC Divide Option
The OSC divide option provides a maximum 1MHz system clock (F_SYS). F_OSC which is
generated in oscillation circuit is divided eight or non-divide to produce F_SYS.
This dividing ratio will be selected by mask option.
F_OSC : Oscillator clock, F_SYS : System clock (F_OSC or F_OSC/8)
OSC
DIVIDE-8
Figure 6-7 OSC Divide Option
7. Electrical Specifications
7.1 Absolute maximum ratings
Symbols
V_DD
V_I
V_O
T _OPR
T _STG
Parameters
Supply Voltage
Input Voltage
Output Voltage
Operating temperature
Storage Temperature
Conditions
Ta=25
-
-
Ratings
-0.3 ~ 6.0
-0.3 ~ V_DD + 0.3
-0.3 ~ V_DD + 0.3
-20 ~ 85
-40 ~ 125
Units
V
V
V
KSI-W002-000
14