SD6830 Datasheet, PDF (12/34 Pages) AUK corp – 4BIT MICROCONTROLLER

SD6830
6.11 Watchdog timer (WDT)
The watchdog timer provides the means to return to a reset condition when a system
malfunction occurs and the program enters an infinite loop caused by noise or any
abnormal state.
Also this timer have a function of oscillation stabilization timer. This is a 13-bit counter,
counts the clock which is divided twelve (F_SYS/12). In the stop mode the oscillation circuit
stops but when a key input is detected (Port D, Port E) oscillation starts. When 12288 clock
cycles have been counted, the program will be executed from reset address (000H). If the
port C data register’s value does not change from “L” to “H” before the timer counts 98304
clock cycles, a device reset condition is generated.
The oscillator stabilization time : 12/F_SYS * 2¹⁰ = 1/F_SYS * 12288 = 27mS (@455KHz)
The time-out period
: 12/F_SYS * 2¹³ = 1/F_SYS * 98304 = 216mS (@455KHz)
Figure 6-4. Function of Watchdog Timer
KSI-W002-000
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