ATMEGA48P_11 Datasheet, PDF (99/420 Pages) ATMEL Corporation – 131 Powerful Instructions - Most Single Clock Cycle Execution

ATmega48P/88P/168P
the pin is set to output. The waveform generated will have a maximum frequency of f_OC0 =
f_{clk_I/O}/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
equation:
f_OCnx
=
-----------------^f--^c--^l--^k--^_--^I--^/-^O-------------------
2 ⋅ N ⋅ (1 + OCRnx)
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
15.7.3
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-
inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match
between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the out-
put is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 15-6. The TCNT0 value is in the timing diagram shown as a his-
togram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare
matches between OCR0x and TCNT0.
Figure 15-6. Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
8025M–AVR–6/11
TCNTn
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
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