ATMEGA168_14 Datasheet, PDF (99/377 Pages) ATMEL Corporation – High endurance non-volatile memory segments

ATmega48/88/168
symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up-
counting Compare Match
• The timer starts counting from a value higher than the one in OCRnx, and for that reason
misses the Compare Match and hence the OCnx change that would have happened on the
way up
15.8
Timer/counter timing diagrams
The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set. Figure 15-8 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 15-8. Timer/counter timing diagram, no prescaling.
clk_I/O
clk_Tn
(clk_I/O/1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 15-9 shows the same timing data, but with the prescaler enabled.
Figure 15-9. Timer/counter timing diagram, with prescaler (f_{clk_I/O}/8).
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
MAX - 1
MAX
BOTTOM
TOVn
BOTTOM + 1
Figure 15-10 on page 100 shows the setting of OCF0B in all modes and OCF0A in all modes
except CTC mode and PWM mode, where OCR0A is TOP.
99
2545T–AVR–05/11