ATMEGA168_14 Datasheet, PDF (193/377 Pages) ATMEL Corporation – High endurance non-volatile memory segments

ATmega48/88/168
• Bits 5:4 – UPMn1:0: Parity mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 20-5. UPMn bits settings.
UPMn1
UPMn0
0
0
0
1
1
0
1
1
Parity mode
Disabled
Reserved
Enabled, even parity
Enabled, odd parity
• Bit 3 – USBSn: Stop bit select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 20-6.
USBS bit settings.
USBSn
0
1
Stop bit(s)
1-bit
2-bit
• Bit 2:1 – UCSZn1:0: Character size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 20-7. UCSZn bits settings.
UCSZn2
UCSZn1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
UCSZn0
0
1
0
1
0
1
0
1
Character size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
• Bit 0 – UCPOLn: Clock polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
2545T–AVR–05/11
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