AT90PWM81_14 Datasheet, PDF (99/327 Pages) ATMEL Corporation – Data and non-volatile program memory

AT90PWM81/161
11.8.4 TIMSK1 - Timer/Counter1 Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
–
–
ICIE1
–
–
–
–
TOIE1
TIMSK1
Read/Write
R
R
R/W
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the AT90PWM81/161, and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see Table 8-1 on page 62) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3, 2,1 – Res: Reserved Bits
These bits are unused bits in the AT90PWM81/161, and will always read as zero.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(see Table 8-1 on page 62) is executed when the TOV1 Flag, located in TIFR1, is set.
11.8.5 TIFR1 - Timer/Counter1 Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
–
–
ICF1
–
–
–
–
TOV1
TIFR1
Read/Write
R
R
R/W
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the AT90PWM81/161, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4, 3, 2,1 – Res: Reserved Bits
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WG.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
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