ATXMEGA256A3_10 Datasheet, PDF (97/110 Pages) ATMEL Corporation – 8/16-bit AVR XMEGA A3 Microcontroller

8068R–AVR–08/10
XMEGA A3
7. DAC refresh may be blocked in S/H mode
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workarund
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
8 BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
9 Both DFLLs and both oscillators has to be enabled for one to work
In order to use the automatic runtime calibration for the 2 MHz or the 32MHz internal oscilla-
tors, the DFLL for both oscillators and both oscillators has to be enabled for one to work.
Problem fix/Workaround
Enable both the DFLLs and both oscillators when using automatic runtime calibration for
one of the internal oscillators.
10 Operating Frequency and Voltage Limitation
To ensure correct operation, there is a limit on operating frequency and voltage. Figure 36-1
on page 97 shows the safe operating area.
Figure 36-1. Operating Frequnecy and Voltage Limitation
MHz
30
15
Safe operating
area
2.4
3.6
V
Problem fix/Workaround
None, avoid using the device outside these frequnecy and voltage limitations.
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