ATXMEGA256A3_10 Datasheet, PDF(59/110 Page) ATMEL Corporation – 8/16-bit AVR XMEGA A3 Microcontroller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ATXMEGA256A3_10 Datasheet, PDF (59/110 Pages) ATMEL Corporation – 8/16-bit AVR XMEGA A3 Microcontroller

◁

XMEGA A3

Mnemonics

LD

LDD

LD

LD

LD

LDD

STS

ST

ST

ST

ST

ST

ST

STD

ST

ST

ST

STD

LPM

LPM

LPM

ELPM

ELPM

ELPM

SPM

SPM

IN

OUT

PUSH

POP

LSL

LSR

Operands

Rd, -Y

Rd, Y+q

Rd, Z

Rd, Z+

Rd, -Z

Rd, Z+q

k, Rr

X, Rr

X+, Rr

-X, Rr

Y, Rr

Y+, Rr

-Y, Rr

Y+q, Rr

Z, Rr

Z+, Rr

-Z, Rr

Z+q,Rr

Rd, Z

Rd, Z+

Rd, Z

Rd, Z+

Z+

Rd, A

A, Rr

Rr

Rd

Rd

Rd

Description

Operation

Load Indirect and Pre-Decrement

Y â Y-1

Rd â (Y)

Load Indirect with Displacement

Rd â (Y + q)

Load Indirect

Rd â (Z)

Load Indirect and Post-Increment

Rd â (Z),

Z â Z+1

Load Indirect and Pre-Decrement

Z â Z - 1,

Rd â (Z)

Load Indirect with Displacement

Rd â (Z + q)

Store Direct to Data Space

(k) â Rd

Store Indirect

(X) â Rr

Store Indirect and Post-Increment

(X) â Rr,

X â X+1

Store Indirect and Pre-Decrement

X â X - 1,

(X) â Rr

Store Indirect

(Y) â Rr

Store Indirect and Post-Increment

(Y) â Rr,

Y â Y+1

Store Indirect and Pre-Decrement

Y â Y - 1,

(Y) â Rr

Store Indirect with Displacement

(Y + q) â Rr

Store Indirect

(Z) â Rr

Store Indirect and Post-Increment

(Z) â Rr

Z â Z+1

Store Indirect and Pre-Decrement

Z â Z-1

Store Indirect with Displacement

(Z + q) â Rr

Load Program Memory

R0 â (Z)

Load Program Memory

Rd â (Z)

Load Program Memory and Post-Increment

Rd â (Z),

Z â Z+1

Extended Load Program Memory

R0 â (RAMPZ:Z)

Extended Load Program Memory

Rd â (RAMPZ:Z)

Extended Load Program Memory and Post-

Increment

Rd â (RAMPZ:Z),

Z â Z+1

Store Program Memory

(RAMPZ:Z) â R1:R0

Store Program Memory and Post-Increment

by 2

(RAMPZ:Z) â R1:R0,

Z â Z+2

In From I/O Location

Rd â I/O(A)

Out To I/O Location

I/O(A) â Rr

Push Register on Stack

STACK â Rr

Pop Register from Stack

Rd â STACK

Bit and Bit-test Instructions

Logical Shift Left

Rd(n+1) â Rd(n),

Rd(0) â 0,

C â Rd(7)

Logical Shift Right

Rd(n) â Rd(n+1),

Rd(7) â 0,

C â Rd(0)

Flags

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

#Clocks

2(1)(2)

2(1)(2)

1(1)(2)

1(1)(2)

2(1)(2)

2(1)(2)

2(1)

1(1)

1(1)

2(1)

1(1)

1(1)

2(1)

2(1)

1(1)

1(1)

2(1)

2(1)

3

3

3

3

3

3

-

-

1

1

1(1)

2(1)

Z,C,N,V,H

1

Z,C,N,V

1

59

8068RâAVRâ08/10

▷