ATTINY261A_1 Datasheet, PDF (94/292 Pages) ATMEL Corporation – 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash

12.6
Dead Time Generator
The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving
external power control switches safely. The Dead Time Generator is a separate block that can
be used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary
output pairs OC1x and OC1x when the PWM mode is enabled and the COM1x1:0 bits are set to
“01”. See Figure 12-7 below.
Figure 12-7. Block Diagram of Waveform Generator and Dead Time Generator.
top
bottom
FOCn
Waveform Generator
OCWnx
OCnx
Dead Time Generator
OCnx
OCnx
pin
OCnx
pin
PWMnx WGM10 COMnx
CK OR PCK
CLOCK
DTPSn
DTnH
DTnL
The tasks are shared as follows: the Waveform Generator generates the output (OCW1x) and
the Dead Time Generator generates the non-overlapping PWM output pair from the output.
Three Dead Time Generators are provided, one for each PWM output. The non-overlap time is
adjustable and the PWM output and it’s complementary output are adjusted separately, and
independently for both PWM outputs.
The Dead Time Generation is based on 4-bit down counters that count the dead time, as shown
in Figure 12-8.
Figure 12-8. Dead Time Generator
CK OR PCK
CLOCK
DEAD TIME
PRE-SCALER
CLOCK CONTROL
COMPARATOR
4-BIT COUNTER
PWM1X
OCnx
OCnx
OCWnx
TCCRnB REGISTER
DTn I/O REGISTER
PWM1X
DATA BUS (8-bit)
There is a dedicated prescaler in front of the Dead Time Generator that can divide the
Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of dead times
that can be generated. The prescaler is controlled by two control bits DTPS11:10. The block has
also a rising and falling edge detector that is used to start the dead time counting period.
Depending on the edge, one of the transitions on the rising edges, OC1x or OC1x is delayed
until the counter has counted to zero. The comparator is used to compare the counter with zero
and stop the dead time insertion when zero has been reached. The counter is loaded with a 4-bit
DT1H or DT1L value from DT1 I/O register, depending on the edge of the Waveform Output
(OCW1x) when the dead time insertion is started. The Output Compare Output are delayed by
one timer clock cycle at minimum from the Waveform Output when the Dead Time is adjusted to
94 ATtiny261A/461A/861A
8197A–AVR–10/09