ATA8741_14 Datasheet, PDF (93/215 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

• Bit 0– TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the status register is set, the timer/counter0 overflow interrupt is
enabled. The corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the TOV0 bit is set in the
timer/counter 0 interrupt flag register – TIFR0.
20.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
Bit
7
6
5
4
3
0x38 (0x58)
–
–
–
–
–
Read/Write
R
R
R
R
R
Initial Value
0
0
0
0
0
2
OCF0B
R/W
0
1
OCF0A
R/W
0
0
TOV0
R/W
0
TIFR0
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the Atmel^® ATtiny24/44/84 and will always read as zero.
• Bit 2– OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a compare match occurs between the timer/counter and the data in OCR0B – output compare
register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (timer/counter compare B match
interrupt enable), and OCF0B are set, the timer/counter compare match interrupt is executed.
• Bit 1– OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a compare match occurs between the timer/counter0 and the data in OCR0A – output compare
register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A
is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (timer/counter0 compare match interrupt
enable), and OCF0A are set, the timer/counter0 compare match interrupt is executed.
• Bit 0– TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in timer/counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-
bit, TOIE0 (timer/counter0 overflow interrupt enable), and TOV0 are set, the timer/counter0 overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. See Table 20-8 on page 90.
ATA8741 [DATASHEET]
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