ATA8741_14 Datasheet, PDF (84/215 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A flag. If the interrupt
is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to
BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does
not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the
counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around
starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare
match by setting the compare output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the
port pin unless the data direction for the pin is set to output. The waveform generated will have
a maximum frequency of ₀ = f_{clk_I/O}/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
equation:
f_OCnx = -2----_â‹---_N------_â‹---₍^f--^c_1--^l-^k-+--^_--^I-_O-^/-^O---_C----_R----_n----_x---₎
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts
from MAX to 0×00.
20.7.3 Fast PWM Mode
The fast pulse width modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform
generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from
BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0×FF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7.
In non-inverting compare output mode, the output compare (OC0x) is cleared on the compare match between TCNT0 and
OCR0x, and set at BOTTOM. In inverting compare output mode, the output is set on compare match and cleared at
BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the
phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for
power regulation, rectification, and DAC applications. High frequency allows physically small sized external components
(coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at
the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 20-6. The TCNT0 value is in
the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x
and TCNT0.
Figure 20-6. Fast PWM Mode, Timing Diagram
OCRnx Interrupt
Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
TCNTn
OCnx
OCnx
Period
1
2
3
4
5
6
7
(COMnx1:0 = 2)
(COMnx1:0 = 3)
84 ATA8741 [DATASHEET]
9140E–INDCO–09/14