AT89C5130A-M_14 Datasheet, PDF (93/188 Pages) ATMEL Corporation – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode

AT89C5130A/31A-M
19. Serial Peripheral Interface (SPI)
The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communica-
tion between the MCU and peripheral devices, including other MCUs.
19.1 Features
Features of the SPI module include the following:
• Full-duplex, three-wire synchronous transfers
• Master or Slave operation
• Eight programmable Master clock rates
• Serial clock with programmable polarity and phase
• Master mode fault error flag with MCU interrupt capability
• Write collision flag protection
19.2
Signal Description
Figure 19-1 shows a typical SPI bus configuration using one Master controller and many Slave
peripherals. The bus is made of three wires connecting all the devices:
Figure 19-1. SPI Master/Slaves Interconnection
MISO
MOSI
SCK
SS
VDD
Master
0
1
2
3
Slave 1
Slave 4
Slave 3
Slave 2
19.2.1
19.2.2
The Master device selects the individual Slave devices by using four pins of a parallel port to
control the four SS pins of the Slave devices.
Master Output Slave Input (MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI
line is used to transfer data in series from the Master to the Slave. Therefore, it is an output sig-
nal from the Master, and an input signal to a Slave. A byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave Output (MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO
line is used to transfer data in series from the Slave to the Master. Therefore, it is an output sig-
nal from the Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
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