ATMEGA324P-B_14 Datasheet, PDF (92/344 Pages) ATMEL Corporation – 8-bit Atmel Microcontroller with 16/32/64Kbytes In-system Programmable Flash

The double buffered output compare registers (OCRnA/B/C) are compared with the Timer/Counter value at all time. The
result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output
compare pin (OCnA/B/C). Section 16.7 “Output Compare Units” on page 98. The compare match event will also set the
compare match flag (OCFnA/B/C) which can be used to generate an output compare interrupt request.
The input capture register can capture the Timer/Counter value at a given external (edge triggered) event on either the input
capture pin (ICPn) or on the analog comparator pins (Section 22. “AC - Analog Comparator” on page 204) The input capture
unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA
register, the ICRn register, or by a set of fixed values. When using OCRnA as TOP value in a PWM mode, the OCRnA
register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing
the TOP value to be changed in run time. If a fixed TOP value is required, the ICRn register can be used as an alternative,
freeing the OCRnA to be used as PWM output.
16.2.2 Definitions
The following definitions are used extensively throughout the section:
Table 16-1. Definitions
Parameter Definition
BOTTOM
The counter reaches the BOTTOM when it becomes 0x0000.
MAX
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP
value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in
the OCRnA or ICRn register. The assignment is dependent of the mode of operation.
16.3
Accessing 16-bit Registers
The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR^® CPU via the 8-bit data bus. The
16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for
temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers
within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a
16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied
into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the
16-bit register is copied into the temporary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCRnA/B/C 16-bit registers does not
involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the
high byte.
92 ATmega164P-B/ATmega324P-B/ATmega644P-B [DATASHEET]
9255E–AVR–08/14