ATMEGA324P-B_14 Datasheet, PDF (18/344 Pages) ATMEL Corporation – 8-bit Atmel Microcontroller with 16/32/64Kbytes In-system Programmable Flash

8.4 EEPROM Data Memory
The ATmega164P-B/324P-B/644P-B contains 512/1/2Kbytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase
cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM address
registers, the EEPROM data register, and the EEPROM control register.
For a detailed description of SPI, JTAG and parallel data downloading to the EEPROM, see Section 27.6 “Parallel
Programming Parameters, Pin Mapping, and Commands” on page 259, Section 27.8 “Serial Downloading” on page 270, and
Section 27.10 “Programming via the JTAG Interface” on page 274 respectively.
8.4.1
EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space. See Section 8.6 “Register Description” on page 19 for
details. The write access time for the EEPROM is given in Table 8-2 on page 21. A self-timing function, however, lets the
user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some
precautions must be taken. In heavily filtered power supplies, V_CC is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section 8.4.2 “Preventing EEPROM Corruption” on page 18 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the
EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the
EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
8.4.2
Preventing EEPROM Corruption
During periods of low V_CC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the
EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design
solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to
the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly,
if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the
internal brown-out detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an
external low V_CC reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.
8.5 I/O Memory
The I/O space definition of the ATmega164P-B/324P-B/644P-B is shown in Section 30. “Register Summary” on page 323.
All ATmega164P-B/324P-B/644P-B I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by
the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the
I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction
set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be
used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
The ATmega164P-B/324P-B/644P-B is a complex microcontroller with more peripheral units than can be supported within
the 64 location reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
18 ATmega164P-B/ATmega324P-B/ATmega644P-B [DATASHEET]
9255E–AVR–08/14