TSC21020F_14 Datasheet, PDF (9/50 Pages) ATMEL Corporation – Off-Chip Harvard Architecture Maximizes Signal Processing Performance

System Interface
TSC21020F
Figure 2 shows an TSC21020F basic system configuration.
The external memory interface supports memory- mapped peripherals and slower mem-
ory with a user-defined combination of programmable wait states and hardware
acknowledge signals. Both the program memory and data memory interfaces support
addressing of page-mode DRAMs.
The TSC21020F's internal functions are supported by four internal buses: the program
memory address (PMA) and data memory address (DMA) buses are used for
addresses associated with program and data memory. The program memory data
(PMD) and data memory data (DMD) buses are used for data associated with the two
memory spaces. These buses are extended off chip. Four data memory select (DMS)
signals select one of four user-configurable banks of data memory. Similarly, two pro-
gram memory select (PMS) signals select between two user-configurable banks of
program memory. All banks are independently programmable for 0-7 wait states.
The PX registers permit passing data between program memory and data memory
spaces. They provide a bridge between the 48-bit PMD bus and the 40-bit DMD bus or
between the 40-bit register file and the PMD bus.
The PMA bus is 24 bits wide allowing direct access of up to 16M words of mixed instruc-
tion code and data. The PMD is 48 bits wide to accommodate the 48-bit instruction
width. For access of 40-bit data the lower 8 bits are unused. For access of 32-bit data
the lower 16 bits are ignored.
The DMA bus is 32 bits wide allowing direct access of up to 4 Gigawords of data. The
DMD bus is 40 bits wide. For 32-bit data, the lower 8 bits are unused. The DMD bus pro-
vides a path for the contents of any register in the processor to be transferred to any
other register or to any external data memory location in a single cycle. The data mem-
ory address comes from one of two sources: an absolute value specified in the
instruction code (direct addressing) or the output of a data address generator (indirect
addressing).
Figure 2. Basic System Configuration
4153H–AERO–04/07
External devices can gain control of the processor's memory buses from the
TSC21020F by means of the bus request/grant signals (BR and BG). To grant its buses
in response to a bus request, the TSC21020F halts internal operations and places its
9