TSC21020F_14 Datasheet, PDF (1/50 Pages) ATMEL Corporation – Off-Chip Harvard Architecture Maximizes Signal Processing Performance

Features
• Superscalar IEEE Floating-Point-Processor
• Off-Chip Harvard Architecture Maximizes Signal Processing Performance
• 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution
• 60 MFLOPS Peak, 40 MFLOPS Sustained Performance
• 1024-Point Complex FFT Benchmark: 0.975 ms
• Divide (y/x): 300 ns
• Inverse Square Root (1/ /x): 450 ns
• 32-bit Single-Precision and 40-bit Extended-Precision IEEE Floating-Point Data
Formats
• 32-bit Fixed-Point Formats, Integer and Fractional, with 80-bit Accumulators
• IEEE Exception Handling with Interrupt on Exception
• Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter
• Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse
Addressing Modes
• Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle
Multiply and ALU Operations
• Multiply with Add and Subtract for FFT Butterfly Computation
• Efficient Program Sequencing with Zero Overhead Looping: Single-Cycle Loop Setup
• Single-Cycle Register File Context Switch
• 23ns External RAM Access Time for Zero-Wait-State, 40 ns Instruction Execution
• IEEE JTAG Standard 1149.1 Test Access Port and On-chip Emulation Circuitry
• 223 CPGA package for breadboarding
• 256 Multi-layer Quad Flat Pack, Flat Leads, For Flight Models
• Fully compatible with Analog Devices ADSP-21020
• No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm²
• Tested up to a Total Dose of 100 krads (Si) according to MIL STD 883 Method 1019
• SEU Error Note in GEO Orbit Better than 5E^-7 Error/Device/Day (worst case)
• For 25 MHz Specification, Contact Atmel for Availability
• Quality Grades - ESCC with 9512/002 and QML-Q or V with 5962-99539
Introduction
Atmel is manufacturing a radiation hard version of the Analog Devices ADSP-21020
32/40-bit Floating-Point DSP.
The product is pin and code compatible with ADI product, making system develop-
ment straight forward and cost effective, using existing development tools and
algorithms.
Notes: 1. Design using patent from INPG-CNRS Denis BESSOT/Raoul VELAZCO
2. Product licensed from Analog Devices Inc.
Rad. Hard
32/40-bit IEEE
Floating Point
DSP
TSC21020F
Rev. 4153I-AERO–04/07
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