AT24C256B_07 Datasheet, PDF(9/21 Page) ATMEL Corporation – Two-wire Serial EEPROM 256K (32,768 x 8)

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AT24C256B_07 Datasheet, PDF (9/21 Pages) ATMEL Corporation – Two-wire Serial EEPROM 256K (32,768 x 8)

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Write

Operations

AT24C256B

BYTE WRITE: A write operation requires two 8-bit data word addresses following the device

address word and acknowledgment. Upon receipt of this address, the EEPROM will again

respond with a â0â and then clock in the first 8-bit data word. Following receipt of the 8-bit data

word, the EEPROM will output a â0â. The addressing device, such as a microcontroller, must

then terminate the write sequence with a stop condition. At this time the EEPROM enters an

internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this

write cycle and the EEPROM will not respond until the write is complete (see Figure 8).

Figure 8. Byte Write

Note: * = DONâT CARE bit

PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not send a

stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges

receipt of the first data word, the microcontroller can transmit up to 63 more data words. The

EEPROM will respond with a â0â after each data word received. The microcontroller must ter-

minate the page write sequence with a stop condition (see Figure 9).

Figure 9. Page Write

Note: * = DONâT CARE bit

The data word address lower six bits are internally incremented following the receipt of each

data word. The higher data word address bits are not incremented, retaining the memory page

row location. When the word address, internally generated, reaches the page boundary, the

following byte is placed at the beginning of the same page. If more than 64 data words are

transmitted to the EEPROM, the data word address will âroll overâ and previous data will be

overwritten. The address âroll overâ during write is from the last byte of the current page to the

first byte of the same page.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a

start condition followed by the device address word. The read/write bit is representative of the

operation desired. Only if the internal write cycle has completed will the EEPROM respond

with a â0â, allowing the read or write sequence to continue.

5080BâSEEPRâ1/07

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