AT24C256B_07 Datasheet, PDF (7/21 Pages) ATMEL Corporation – Two-wire Serial EEPROM 256K (32,768 x 8)

AT24C256B
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
Start Bit
Dummy Clock Cycles
Start Bit
SCL
1
2
3
8
9
Stop Bit
SDA
Figure 4. Bus Timing
Figure 5. Write Cycle Timing
SCL
SDA
8th BIT
ACK
Note:
WORDn
STOP
CONDITION
twr⁽¹⁾
START
CONDITION
1. The write cycle time t_WR is the time from a valid stop condition of a write sequence to the end
of the internal clear/write cycle.
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5080B–SEEPR–1/07