ATTINY48_14 Datasheet, PDF (85/302 Pages) ATMEL Corporation – High Performance, Low Power AVR

ATtiny48/88
Figure 11-7. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 11-8 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode where OCR0A
is TOP.
Figure 11-8. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
(CTC)
OCRnx
TOP - 1
TOP
TOP
BOTTOM
BOTTOM + 1
OCFnx
11.8 8-bit Timer/Counter Register Description
11.8.1 TCCR0A – Timer/Counter Control Register A
Bit
7
6
5
0x25 (0x45)
–
–
–
Read/Write
R
R
R
Initial Value
0
0
0
4
3
2
1
0
–
CTC0
CS02
CS01
CS00
TCCR0A
R
R/W
R/W
R/W
R/W
0
0
0
0
0
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – CTC0: Clear Timer on Compare Match Mode
This bit control the counting sequence of the counter, the source for maximum (TOP) counter
value, see Table 11-2. Modes of operation supported by the Timer/Counter unit are: Normal
mode (counter), Clear Timer on Compare Match (CTC) mode (see “Modes of Operation” on
page 83).
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