ATMEGA32A_1 Datasheet, PDF (71/352 Pages) ATMEL Corporation – 8-bit Microcontroller with 32K Bytes In-System Programmable Flash

ATmega32A
the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logi-
cal one to its Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled.
Table 13-3. Asynchronous External Interrupt Characteristics
Symbol Parameter
Condition Min Typ Max Units
t_INT
Minimum pulse width for asynchronous
external interrupt
50
ns
13.1.3 GICR – General Interrupt Control Register
Bit
7
6
5
4
3
2
1
0
INT1
INT0
INT2
–
–
–
IVSEL
IVCE
GICR
Read/Write
R/W
R/W
R/W
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU
General Control Register (MCUCR) define whether the External Interrupt is activated on rising
and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt
Request 1 is executed from the INT1 interrupt Vector.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
General Control Register (MCUCR) define whether the External Interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 interrupt vector.
• Bit 5 – INT2: External Interrupt Request 2 Enable
When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control2 bit (ISC2) in the MCU Control and
Status Register (MCUCSR) defines whether the External Interrupt is activated on rising or falling
edge of the INT2 pin. Activity on the pin will cause an interrupt request even if INT2 is configured
as an output. The corresponding interrupt of External Interrupt Request 2 is executed from the
INT2 Interrupt Vector.
13.1.4 GIFR – General Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
INTF1
INTF0
INTF2
–
–
–
–
–
GIFR
Read/Write
R/W
R/W
R/W
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bit 7 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set
(one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corre-
sponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
71
8155B–AVR–07/09