ATXMEGA256A3U Datasheet, PDF (7/116 Pages) ATMEL Corporation – 8/16-bit Atmel XMEGA A3U Microcontroller

XMEGA A3U
6. AVR CPU
6.1 Features
6.2 Overview
• 8/16-bit high performance AVR RISC Architecture
– 142 instructions
– Hardware multiplier
• 32x8-bit registers directly connected to the ALU
• Stack in SRAM
• Stack Pointer accessible in I/O memory space
• Direct addressing of up to 16Mbytes of program and 16Mbytes of data memory
• True 16/24-bit access to 16/24-bit I/O registers
• Support for 8-, 16- and 32-bit Arithmetic
• Configuration Change Protection of system critical features
The Atmel^® AVR^® XMEGA^® devices use the 8/16-bit AVR CPU. The main function of the CPU is
to execute the code and perform all calculations. The CPU is able to access memories, perform
calculations, control peripherals, and execute the program from the FLASH memory. Interrupt
handling is described in a separate section, refer to ”Interrupts and Programmable Multi-level
Interrupt Controller” on page 26.
Figure 6-1 on page 7 shows the block diagram of the AVR CPU architecture.
Figure 6-1. Block Diagram of the AVR CPU architecture
8386A–AVR–07/11
In order to maximize performance and parallelism, the AVR uses a Harvard architecture with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
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