ATXMEGA256A3U Datasheet, PDF (69/116 Pages) ATMEL Corporation – 8/16-bit Atmel XMEGA A3U Microcontroller

XMEGA A3U
35.6 ADC Characteristics
Table 35-5. ADC Characteristics
Symbol Parameter
RES
Resolution
Condition⁽²⁾
Min
8
Conversion time (latency)
(RES+2)/2+(GAIN !=0), RES = 8 or 2
5
Clk_ADC
f_ADC
AVCC
VREF
Rin
Cin
R_AREF
C_AREF
Vin
Vin
INL⁽¹⁾
Sampling Time
ADC Clock frequency
Sample rate
Analog supply voltage
Reference voltage
Input resistance
Input capacitance
Reference input resistance
Reference input capacitance
Start-up time
ADC settling time
Input range
Conversion range
Conversion range
Integral non-linearity
1/2 Clk_ADC cycle
Max is 1/4 of Peripheral clock frequency
Measuring internal signals
CURRLIMIT = LOW
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
Switched
Switched
(leackage only)
Static load
ADC clock cycles
After changing reference or input mode
After ADC flush
Differential mode, Vinp - Vinn
Single ended unsigned mode, Vinp
500kSPS
V_CC-1.0V < VREF< V_CC-0.6V
V_CC-1.0V < VREF< V_CC-0.6V
2000kSPS
0.25
100
100
100
100
100
100
V_CC- 0.3
1
-0.1
-VREF
-ΔV
DNL⁽¹⁾ Differential non-linearity
500kSPS,
guaranteed
monotonic
2000kSPS,
guaranteed
monotonic
V_CC-1.0V < VREF< V_CC-0.6V
V_CC-1.0V < VREF< V_CC-0.6V
Offset Error
Temperature drift
Operating voltage drift
Typ
12
4.0
4.4
>10
7
12
7
1
±1.2
±1.5
±1.0
±1.5
±0.8
±0.5
±0.8
±0.5
-2
<0.01
<0.6
Max
12
8
5
2000
125
2000
1500
1000
500
V_CC+ 0.3
AV_CC- 0.6
24
7
1
AV_CC+ 0.1
VREF
VREF-ΔV
2
3
2
3
1.2
Units
Bits
Clk_ADC
cycles
µS
kHz
kSPS
V
kΩ
pF
MΩ
pF
Clk_ADC
cycles
V
LSB
1.5
1.2
1.5
mV
mV/K
mV/V
69
8386A–AVR–07/11