ATMEGA161L_14 Datasheet, PDF (7/159 Pages) ATMEL Corporation – Program and Data Memories

Architectural
Overview
ATmega161(L)
The fast-access Register File concept contains 32 x 8-bit general purpose working reg-
isters with a single clock cycle access time. This means that during one single clock
cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output
from the Register File, the operation is executed and the result is stored back in the
Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the constant table look-up func-
tion. These added function registers are the 16-bit X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 4
shows the ATmega161 AVR RISC microcontroller architecture.
Figure 4. The ATmega161 AVR RISC Architecture
Data Bus 8-bit
8K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registers
ALU
1024 x 8
Data
SRAM
512 x 8
EEPROM
32
I/O Lines
Interrupt
Unit
SPI
Unit
Serial
UART0
Serial
UART1
8-bit
Timer/Counter
with PWM
and RTC
16-bit
Timer/Counter
with PWM
8-bit
Timer/Counter
with PWM
Watchdog
Timer
Analog
Comparator
7
1228D–AVR–02/07