ATMEGA161L_14 Datasheet, PDF (37/159 Pages) ATMEL Corporation – Program and Data Memories

Power-down Mode
Power-save Mode
ATmega161(L)
Analog Comparator interrupt is not required, the Analog Comparator can be powered
down by setting the ACD bit in the Analog Comparator Control and Status Register
(ACSR). This will reduce power consumption in Idle mode.
When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the
Power-down mode. In this mode, the external Oscillator is stopped while the external
interrupts and the Watchdog (if enabled) continue operating. Only an External Reset, a
Watchdog Reset (if enabled), an external level interrupt on INT0 or INT1, or an external
edge interrupt on INT2 can wake up the MCU.
If INT2 is used for wake-up from Power-down mode, the edge is remembered until the
MCU wakes up.
If a level-triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensi-
tive to noise. The changed level is sampled twice by the Watchdog Oscillator clock, and
if the input has the required level during this time, the MCU will wake up. The period of
the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the
Watchdog Oscillator is voltage-dependent as shown in the Electrical Characteristics
section.
When waking up from Power-down mode, a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable
after having been stopped. The wake-up period is defined by the same CKSEL fuses
that define the Reset Time-out period. The wake-up period is equal to the clock counting
part of the reset period, as shown in Table 4. If the wake-up condition disappears before
the MCU wakes up and starts to execute, e.g., a low level on INT0 is not held long
enough, the interrupt causing the wake-up will not be executed.
When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the
Power-save mode. This mode is identical to Power-down, with one exception.
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,
Timer/Counter2 will run during sleep. In addition to the Power-down wake-up sources,
the device can also wake up from either Timer Overflow or Output Compare event from
Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK and the global interrupt enable bit in SREG is set.
If the asynchronous timer is not clocked asynchronously, Power-down mode is recom-
mended instead of Power-save mode because the contents of the register in the
asynchronous timer should be considered undefined after wake-up in Power-save mode
even if AS2 is 0.
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